Revopex

Design & Characterization

As the electronics industry moves towards more complex semiconductor packages that are smaller, faster, and higher performance, engineers are faced with the challenge of trying to fit more powerful components into a smaller area without causing long-term reliability issues or stress on a package. Delivering the optimum package design requires an in-depth analysis of key package measurements and simulation.

Revopex’s worldwide package characterization teams located in US, APAC and Europe countries,provide advanced package characterization services for our global customers to ensure they have high quality, high performance, reliable, and cost-effective package designs that meet their market requirements.

Packaging Services

Revopexoffers a full suite of assembly services to meet our customers’ semiconductor packaging needs, including leadframe, laminate, flip chip interconnect, and advanced wafer level technology.

Revopexdifferentiates itself by providing a comprehensive platform of wafer level technology that includes Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD), and Through Silicon Via (TSV) to meet the increasing market demand for next-generation devices with higher levels of integration, increased functionality, and compact sizes.

We collaborate with customers on die and package designs to provide the best possible products in terms of performance, quality, cycle time, and cost. Our comprehensive wafer level technology platform provides customers with a wide range of choices for 2.5D and 3D package integration in advanced mobile devices such as smartphones and tablets.

Wafer Bumping

Wafer bumping technology can provide significant performance, form factor and cost advantages in a semiconductor package. Wafer bumping is an advanced manufacturing process whereby metal solder balls or bumps are formed on the semiconductor wafer prior to dicing. Wafer bumps provide an interconnection between the die and a substrate or printed circuit board in a device. Solder bump composition and dimension depends on a number of factors such as form factor, cost and the electrical, mechanical and thermal performance requirements of the semiconductor device.

Test Services

Semiconductor chips are rapidly increasing in complexity, requiring more advanced test systems and capabilities. Revopexprovides customers with a full suite of test platforms and engineering services to support a broad range of mixed signal, Radio Frequency (RF), analog, and high-performance digital semiconductor devices. Our full turnkey test services, which include wafer bump, probe, final test, post-test, and system level test, deliver the lowest cost of test for our customers with the highest possible throughput and faster time-to-market.